The present invention relates to a computer that performs a calibration on hardware during startup, in particular, performs a timing adjustment of a signal transmission, and also relates to a method of the calibration.
Cell Broadband Engine™ (hereinafter, referred to as a Cell processor) is connected to an XDR™ memory, which is a main memory, and an IO bridge via exclusive interfaces so as to secure high speed data transfer. In a system equipped with plural Cell processors, the Cell processors are connected to each other in the same manner (refer, for example, to “Cell Broadband Engine™ Architecture” (online), Sony Corporation (retrieved on Jan. 21, 2009 from an Internet URL: http://cell.scei.co.jp/pdf/CBE_Architecture_v101_j.pdf) as to a Cell processor, to, for example, “XDR™” (online), Rambus Inc. (retrieved on Jan. 21, 2009 from an Internet URL: http://www.rambus.com/jp/products/xdr/index.html) as to an XDR memory, and to, for example, “FlexPhase™ Timing Adjustments” (online), Rambus Inc. (retrieved on Jan. 21, 2009 from an Internet URL: http://www.rambus.com/jp/patents/innovations/detail/flexpha se_timing.html) as to the interface).
Having such connections between devices, a computer system (hereinafter, referred to simply as a “system”) equipped with a Cell processor makes a timing adjustment of a signal transmission, which is called a calibration, after being powered on for startup (refer to, for example, “Cell Broadband Engine CMOS SOI 90 nm Hardware Initialization Guide” (online), International Business Machines Corporation (retrieved on Jan. 21, 2009 from an Internet URL: http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/BD 3F1F4C3 DB32C7487257142006131BC)). Accordingly, signals subjected to the calibration are:
(1) signals transmitted between the Cell processor and an XDR memory;
(2) signals transmitted between the Cell processor and an IO bridge; and
(3) signals transmitted between a Cell processor and another Cell processor (in a case where the system is equipped with plural Cell processors).
An appropriate timing of a signal transmission may vary greatly depending on individual difference among devices and on the surrounding temperature. The calibration is therefore executed every time the system is powered on.
In the calibration performed during startup of the system equipped with a Cell processor, an operation clock of the system is calibrated by transmitting signals having a specific pattern between any two of the Cell processor, XDR memory, and the IO bridge. Here, if the adjustments are repeatedly made by use of signals having various patterns, accuracy of the calibration is enhanced. On the other hand, the adjustments by use of the signals having such various patterns requires a longer time. That is, the more accurate calibration takes longer time. Therefore, the calibration with reduced time sacrifices the calibration accuracy. Here, the time required for the calibration considerably affects a startup time of the system, since the calibration is performed at every system startup.
Furthermore, a time required for the calibration linearly increases as a capacity of a memory included in a system becomes larger. In other words, a system having a larger memory capacity requires a longer time for the calibration, and accordingly requires a longer time for the system startup. In order to reduce a system startup time, there has been so far no choice but to reduce the calibration accuracy to reduce the time required for the calibration.
Note that, while a system equipped with a Cell processor is described here, any other system requiring hardware calibration during startup can be considered as having the same problem.